Certain integrated circuits (ICs) and IC fabrication processes utilize local interconnects to electrically couple transistor elements. Local interconnects can connect a drain, source, or gate of one transistor to a drain, source, or gate of another transistor. Additionally, local interconnects can connect the drain, source, or gate of one transistor to the drain, source, or gate of the same transistor or to other circuits or conductors within the IC. Generally, conventional local interconnects are formed below a first aluminum (Al) or metal layer associated with an IC (e.g., at the same level or below the top surface of a first thick insulating layer over the semiconductor substrate).
Local interconnects can be created in a trench etch and fill process before the first metal layer is provided over the first thick insulating layer. Local interconnects are generally formed after transistors are formed on the semiconductor substrate and covered by the first thick insulating layer. The thick insulating layer is etched to form trenches which connect the various circuit and transistor elements in accordance with the particular design of the IC. The trenches are filled with a conductive material, such as, polysilicon, tungsten, or other metal to complete the local interconnect. In this way, connections between transistors, nodes, and other elements can be achieved locally without using the first metal layer.
With the demand for higher levels of integration in semiconductor chips, such as silicon semiconductor chips, and the need for greater density in the circuits on the chips, the spacing between the gates of field effect transistors (FET) when forming local interconnects to the source and drain of the FET becomes more and more critical. This is especially the case with a microprocessor IC or chip of which a large portion of the real estate of the chip is a static random access memory (SRAM). For increased performance of future microprocessors, the storage capacity of the SRAM must increase, thereby requiring a larger portion of real estate of the microprocessor.
Since the FET is fabricated prior to the formation of the local interconnects, conventional processes include a lithographic mask design which provides for additional space between local interconnect openings and the polysilicon gate to prevent accidental shorting of the source and/or drain to the gate across the local interconnect. This additional space in the layout or mask design wastes valuable real estate of the silicon wafer. Therefore, it would be desirable to create minimum spaced local interconnects without regard to the presence of the gate of the FET in the spaces between the local interconnects.